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Integrated Circuit Systems, Inc.
ICS9250-22
Frequency Generator for P IVTM
Recommended Application: P IV Chipset Support Output Features: * 4 Differential CPU Clock Pairs @ 3.3V * 2 - 3V MREF clocks for memory reference seeds, (separate single ended but 180 degrees out of phase) * 4 - 66MHz reference output * 10 - 3V 33MHz PCI clocks * 2 - 48MHz clocks * 2 - 14.318 reference output Features: * Support power management: Power Down Mode * Supports Spread Spectrum modulation: 0 to -0.5% down spread. * Uses external 14.318MHz crystal * Select logic for Differential Swing Control, Test mode, Tristate, Power down, Spread Spectrum, limited frequency select, selective clock enable. * External resistor for current reference * FS pins for frequency select Key Specifications: * 3V66 Output jitter <300ps * CPU Output Jitter <200ps * MREF Output jitter <250ps
Pin Configuration
GND MULTSEL0/REF MULTSEL1/REF VDDREF X1 X2 GNDREF PCICLK0 PCICLK1 VDDPCI PCICLK2 PCICLK3 GNDPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI PCICLK8 PCICLK9 VDDPCI SEL100/133 GND48 FS0/48MHz FS1/48MHz VDD48 PD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDMREF 3VMREF 3VMREF_B GNDMREF SPREAD# CPUCLKST3 CPUCLKSC3 VDDCPU CPUCLKST2 CPUCLKSC2 GNDCPU CPUCLKST1 CPUCLKSC1 VDDCPU CPUCLKST0 CPUCLKSC0 GNDCPU I REF VDDA GNDA VDD3V66 3V66-3 3V66-2 GND3V66 GND3V66 3V66-1 3V66-0 VDD3V66
56-Pin 300mil SSOP & TSSOP
Functionality
SEL133/ 100 0 0 0 0 1 1 1 1 FS0 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 Function Active 100MHz (Reserved) (Reserved) Tristate all outputs Active 133MHz (Reserved) (Reserved) Test Mode
3VMREF DIVDER
Block Diagram
PLL2
2
ICS9250-22
48MHz
X1 X2
XTAL OSC PLL1 Spread Spectrum
2
REF
CPU DIVDER
4 4
CPUCLKST (3:0) CPUCLKSC (3:0)
3VMREF 3VMREF_B
Power Groups
VDDREF, GNDREF= REF, X1, X2 VDDPCI, GNDPCI = PCICLK VDD48, GND48 = 48MHz, PLL2 VDD3V66, GND3V66=3V66 VDDCPU, GNDCPU = CPUCLK VDDMREF, GNDMREF=3VMREF, 3VMREF_B VDDA=VDD (core supply voltage 3.3V) GNDA=Ground for core supply
9250-22 Rev B 12/08/00 Third party brands and names are the property of their respective owners.
PD# SPREAD# MULTSEL (1:0) SEL100/133 FS(1:0)
Control Logic Config. Reg.
3V66 DIVDER
4
PCI DIVDER
10
PCICLK (9:0)
3V66 (3:0)
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9250-22
General Description
The ICS9250-22 is a single chip clock solution. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-22 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER
1, 7, 13, 19, 24, 32, 33, 37, 40, 46, 53 3, 2 4, 10, 16, 22, 27, 29, 36, 38, 43, 49, 56 5 6 21, 20, 18, 17, 15, 14, 12, 11, 9, 8 23 26, 25 28 35, 34, 31, 30 39 51, 48, 45, 42 50, 47, 44, 41
PIN NAME
GND REF/MULTSEL (1:0) VDD X1 X2 PCICLK (9:0) SEL100/133 FS (1:0) 48MHz PD# 3V66 (3:0) I REF CPUCLKST (3:0) CPUCLKSC (3:0)
TYPE
PWR IN PWR X2 Crystal Input
DESCRIPTION
Ground pins for 3.3V supply MULTSEL0 and MULTSEL1 inputs are sensed on power-up and then internally latched prior to the pin being used for output on 3V 14.318MHz clocks. 3.3V power supply 14.318MHz Crystal input
X1 Crystal Output 14.318MHz Crystal output OUT IN IN OUT IN OUT OUT OUT OUT PCI clock outputs CPU Frequency Select. Low=100MHz, High=133MHz Frequency select pins 48MHz clock output Invokes power-down mode. Active Low. 66MHz reference clocks This pin establishes the reference current for the CPUCLK pairs. This pin takes a fixed precision resistor tied to ground in order to establish the appropriate current. "True" clocks of differential pair CPU outputs. These are switched current outputs and external resistors are required for voltage bias. "Complementory" clocks of differential pair CPU outputs. These are switched current outputs and external resistors are required for voltage bias. Invokes Spread Spectrum functionality on the Differential host clocks, MRef/MRef_b clocks, 66MHz clocks, and 33MHz PCI clocks. Active Low 3V reference to memory clock driver (out of phase with 3Vmref) 3V reference to memory clock driver
52 54 55
SPREAD# 3VMREF_B 3VMREF
IN OUT OUT
Third party brands and names are the property of their respective owners.
2
ICS9250-22
Truth Table
SEL 133/100 0 0 0 0 1 1 1 1 FS0 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 CPU 100MHz N/A N/A Tristate 133MHz N/A N/A TCLK/2 MRef 50MHz N/A N/A Tristate 66MHz N/A N/A TCLK/4 3V66 66MHz N/A N/A Tristate 66MHz N/A N/A TCLK PCI 33MHz N/A N/A Tristate 33MHz N/A N/A TCLK/6 48MHz 48MHz N/A N/A Tristate 48MHz N/A N/A REF 14.318MHz N/A N/A Tristate 14.318MHz N/A N/A TCLK
Group Offset Limits
Group CPU to 3V66 CPU to PCI 3V66 to PCI 1.5 - 3.5ns 3V66 leads 30pF 1.5V Offset No Requirement Measurement Loads (lumped) Measure Points
Third party brands and names are the property of their respective owners.
3
ICS9250-22
CPUCLK Buffer Configuration
Conditions Iout Vdd = nominal (3.30V) Configuration All combinations of M0, M1 and Rr shown in table below All combinations of M0, M1 and Rr shown in table below Load Nominal test load for given configuration Nominal test load for given configuration Min -7% I nominal Max +7% I nominal
Iout
Vdd = 3.30 5%
-12% I nominal +12% I nominal
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.85V /2 60 0.71V @ 50 0.56V @ 60 0.47V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.90V @ 30 0.75V @ 20 0.60 @ 20 0.5V @ 20 1.05V @ 30 0.84V @ 20
Third party brands and names are the property of their respective owners.
4
ICS9250-22
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors IIL2 Operating Supply IDD3.3OP CL = 0 pF; Select @ 100 MHz Current CL = 0 pF; Input address to VDD or GND Powerdown Current IDD3.3PD Input Frequency Pin Inductance Input Capacitance1 Transition time
1 1
MIN 2 VSS-0.3 -5 -5 -200
TYP
MAX VDD+0.3 0.8 5
UNITS V V A A mA mA MHz nH pF pF pF ms ms ms ns ns
130 35 14.318
250 60 7 5 6 45 3 3 3 10 10
Fi Lpin CIN COUT CINX Ttrans Ts TSTAB tPZH,tPZL tPHZ,tPLZ
VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) 1 1
27
Settling time Clk Stabilization1 Delay1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9250-22
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1 2
MIN
TYP 714 714
MAX UNITS V V mA mA ps ps % ps ps
RDSP2B
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 2.375 V VOL @MIN = 1.2 V, VOL @MAX = 0.3 V VOL = 20%, VOH = 80% VOH = 80%, VOL = 20% VT = 50% VT = 50% VT = 50% 2
RDSN2B VOH2B VOL2B IOH2B2 IOL2B2 tr2B
1 1 1 1
0.4 -27 27 175 175 45 500 500 51 110 110 -27 30 700 700 55 150 200
tf2B
dt2B
tsk2B
tjcyc-cyc1
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 33
MAX UNITS MHz 55 0.55 V -33 38 V mA mA ns ns % ps ps
RDSP11 VOH
1
VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
VOL1 1 IOH IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc1
-33 30 0.5 0.5 45 1.4 1.4 51 270 115
2 2 55 500 500
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9250-22
Electrical Characteristics - MREF/MREF_B
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 33
MAX UNITS MHz 55 0.55 V -33 38 V mA mA ns ns % ps ps
RDSP11 VOH
1
VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
VOL1 1 IOH IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc1
-33 30 0.4 0.4 45 1.4 1.4 51 80 105
1.6 1.6 55 100 250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 20 2.4
TYP 48
MAX UNITS MHz 60 0.4 V -23 27 V mA mA ns ns % ps ps
RDSP11 VOH
1
VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
VOL1 1 IOH 1 IOL tr11 tf11 dt11 tsk11 tjcyc-cyc1
-29 29 1 1 45 2 2 50 205
4 4 55 N/A 1000
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9250-22
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 33
MAX UNITS MHz 55 0.55 V -33 38 V mA mA ns ns % ps ps
RDSP11 VOH
1
VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
VOL1 1 IOH 1 IOL tr11 tf11 dt11 tsk11 tjcyc-cyc1
-33 30 0.5 0.5 45 1.3 1.3 51 85 80
2 2 55 250 300
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 20 2.4
TYP 48
MAX UNITS MHz 60 0.4 V -23 27 V mA mA ns ns % ps ps
RDSP11 VOH
1
VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
VOL1 1 IOH IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc1
-29 29 1 1 45 2 2 54 120
4 4 55 N/A 350
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9250-22
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PD#
MREF MREF_BAR
CPUCLKT CPUCLKC VCO Crystal
Notes: 1. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
Third party brands and names are the property of their respective owners.
9
ICS9250-22
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 56
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 18.288 MAX 18.542 MIN .720
D (inch) MAX .730
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9250yF-22-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
10
ICS9250-22
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.17 1.20 0.15 1.05 0.27 .002 .032 .007 .047 .006 .041 .011
A A1 A2 b c D E E1 e L N aaa VARIATIONS N
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.020 BASIC .018 .30 SEE VARIATIONS 0 8 .004
0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
D mm. MIN 13.90 MAX 14.10 MIN .547
D (inch) MAX .555
7/6/00 Rev B
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
56
MO-153 JEDEC Doc.# 10-0039
Ordering Information
ICS9250yG-22-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
11
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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